1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method of forming a salicide layer in an embedded dynamic random access memory (DRAM).
2. Description of Related Art
An embedded dynamic random access memory (DRAM) has a logic region and a random access memory region (called memory region hereinafter). A gate of a traditional logic region comprises an N-type metal oxide semiconductor field effect transistor (n-MOSFET) formed from N-type doped polysilicon and P-type MOS field effect transistor (p-MOSFET) to form a CMOS structure. The phenomenon of punch through and turnoff characteristics are easily generated in a PMOS with an N-type doped polysilicon gate. Therefore, an NMOS having an N-type polysilicon gate and a dual gate of PMOS having an P-type polysilicon gate are gradually used in the logic region to lower the bad effects mentioned above.
A salicide layer cannot be formed on a source/drain region of an embedded DRAM in order to avoid serious current leakage occurring on the source/drain region of the embedded DRAM. Therefore, a tungsten silicide layer is provided on a polysilicon layer to lower resistance of the gate and to increase conductivity of the gate. However, some problems also arise when a dual gate of the embedded DRAM is formed by the tungsten silicide layer on the polysilicon layer to reduce the resistance of the dual gate, as shown in FIGS. 1A to 1D.
FIGS. 1A to 1D are schematic, cross-sectional views showing a conventional method of fabricating an embedded DRAM. Referring to FIG. 1A, a gate oxide layer 102 and a polysilicon layer 104 are sequentially formed on a substrate 100. Ion implantation steps using N-type ions and P-type ions are respectively performed in the polysilicon layer 104, using a mask. A tungsten silicide layer 106 is formed on the polysilicide layer 104 to increase conductivity of a gate formed in a later process. The tungsten silicide layer 106, a dual gate 108a and a gate 108b are formed by defining the tungsten silicide layer 106, the polysilicon layer 104 and the gate oxide layer 102, as shown in FIG. 1B.
FIG. 2 is a schematic, three-dimensional diagram showing a dual gate 108a and a gate 108b according to FIG. 1B. The dual gate 108a has an N-type polysilicon layer 104a' and a P-type polysilicon layer 104a". The gate 108b has an N-type polysilicon layer 104b. An N-type doped drain (LDD) region 110 and P-type LDD region 110 are respective formed in the substrate 100. Silicon nitride spacers 112 are formed on sidewalls of the gates 108a, 108b. An ion implantation step is performed in the substrate 100 to respectively form an N-type source/drain region 114 and P-type source/drain region 114. A rapid thermal process (RPT) is performed at about 1000.degree. C. to activate ions of the source/drain regions 114.
As shown in FIG. 1C, the substrate 100 is covered with an oxide layer 116. The oxide layer 116 is defined using a mask to make the oxide layer 116 cover only a portion of the substrate 100. The portion not covered with the oxide layer 116 is defined as a logic region 118a, and the other portion covered with the oxide layer 116 is defined as a memory region 118b.
A titanium layer is formed over the substrate 100. A RTP is performed to make the titanium layer to react with the exposed substrate 100. Titanium silicide layers 120 are formed on the exposed source/drain region 114 in the logic region 118a, as shown in FIG. 1D.
In the process mentioned above, the purpose of forming the tungsten silicide layer 106 is to increase conductivity of the polysilicon layer 104. While performing the RTP, the high temperature and larger diffusion coefficient of impurities in the tungsten silicide layer will lead to some bad effects for the dual gate in the logic region. Due to the conditions mentioned above, the N-type impurities in the polysilicon layer 104a' of the dual gate diffuse into the P-type polysilicon layer 104a" through the tungsten silicide layer 106. The P-type impurities in the polysilicon layer 104a" also diffuse into the N-type polysilicon layer 104a' through the tungsten silicide layer 106. Thus, inter-diffusion occurs in the dual gate, as shown in FIG. 2. The inter-diffusion will cause the dual gate to fail.
In addition, a definition step must be performed on the tungsten silicide layer 106 and the polysilicide layer 104 in order to form the gate. It is more difficult to perform the definition step due to the presence of the tungsten silicide layer 104.